The use of copper wiring as interconnects in semiconductor devices has increased dramatically as ground rules shrink in order to prevent capacitance coupling or crosstalk between metal lines. Interconnects are typically formed by a damascene approach in which a metal layer is deposited in an opening etched into one or more dielectric layers on a substrate. An important aspect of the damascene process is planarization of the metal layer which becomes coplanar with the top dielectric layer. A chemical mechanical polish (CMP) step is frequently employed as the preferred method to achieve planarization.
A commercially available CMP tool represented by tool 1 in FIG. 1 is used to perform the planarization process. Tool 1 includes an upper carousel 2 that can rotate about a center post 3 on a center axis 4. Carousel 2 contains four rotatable carrier heads 5 that each holds a wafer 6. The base 7 of the CMP tool 1 is comprised of three polishing stations 8 and a transfer station 9. Each polishing station 8 has a rotatable platen 10 upon which a polishing pad 11 is placed and a mechanism for introducing a chemical slurry (not shown) that aids the polishing process. Typically, a wafer 6 is pressed against a polishing pad and slurry while the head 5 is rotated in one direction and the platen 10 is rotated in the opposite direction. Other parts of the CMP tool 1 are not shown and may include an end point detect system to prevent excessive polishing of a metal or dielectric layer.
The CMP process has been improved by implementing methods to avoid defects such as scratches and dishing on the surface of the metal layer or dielectric layer. As the width and height of metal interconnects becomes smaller in advanced technologies, more emphasis must be placed on a method to minimize variations in copper sheet resistance (Rs) that has a direct bearing on device performance. Currently, there is no manufacturing approach to control copper Rs variations.
A planarization method may involve two or more CMP steps that each require a different slurry which is selective to a particular layer. For instance, in U.S. Pat. No. 6,555,477, separate steps are employed to polish a copper layer, a barrier layer, and an intermetal dielectric (IMD) layer in one sequence. A copper polishing step followed by an oxide buffing step is described in U.S. Pat. No. 6,372,632.
J. Zhang, J. Paik, B. Lusher, B. Brown, S. Huey, M. Sarfaty, A. Shanmugasundram, A. Schwarm, A. Sikora and A. Nickles in “Automated Process Control of Within-Wafer and Wafer-to-Wafer Uniformity in Oxide CMP” [online] March 2002, CMP MIC [retrieved on Jan. 27, 2003] retrieved from URL: http:www.appliedmaterials.com/search97cgi/s97_sgi describes a within wafer closed loop control with feed-forward and feed-backward of data to provide run-to-run control. Here the goal is to control Rs in bulk copper that is later removed by CMP. The Rs of an actual interconnect is not measured and there is no provision to reduce copper sheet resistance variations in the product.
A prior art method for optimizing wafer by wafer processing is found in U.S. Pat. No. 6,405,144 involving input signals that are controlled by feed-forward and feed-backward pathways. Individual recipes are updated by a remote parameter setting command from a central computer. In related art, feed forward threads are based on material groups and a set of rules is applied in a logic program for process control as claimed in U.S. Pat. No. 6,148,239.
In U.S. Pat. No. 6,335,286, a CMP buffing process is controlled by monitoring the scratch count on a process surface and feeding the data back to a process controller. An in-situ non-invasive method of determining physical properties such as sheet resistance and film thickness is provided in U.S. Pat. No. 5,719,495. Still, there is no known algorithm that can be applied to a CMP process to control copper sheet resistance.
Process control is also achieved through test structures as in U.S. Pat. No. 6,528,818 where a system for detecting defects is described and in U.S. Pat. No. 6,514,858 which involves a test structure to monitor CMP polish depth.
Monitor wafers are typically non-product wafers that are inserted into a production scheme in order to verify that process parameters are being maintained within specification. This practice can minimize rework by detecting an unacceptable drift in a process tool operation before a large amount of product wafers are processed incorrectly. However, monitor wafers may be over utilized to the extent that the fabrication method becomes unprofitable because of the loss of production time or down time associated with monitors. Product wafers may be held in queue until a monitor wafer is processed and measured for defects and parameters such as film thickness and uniformity. Therefore, a good automated process control (APC) method should minimize the amount of monitor wafers necessary in a production environment.